In today's integrated circuits, power-consumption is of utmost importance. A main contributor to power-consumption is the standby power due to increasing leakage currents in the deep submicron devices. One way to reduce this leakage and its corresponding power consumption is to reduce the supply voltage of idle parts of the integrated circuit to a minimum voltage level. In Static Random Access Memories, henceforth referred to as SRAMs, standby power consumption becomes more important than dynamic power consumption due to the high density of transistors and their, on the average, low activity. A major issue when reducing the supply voltage of idle parts of the integrated circuit to a minimum voltage level in a SRAM is retaining the data stored in the memory because the supply voltage Vdd cannot be lowered below a minimum voltage level. Lowering the supply voltage Vdd below a certain minimum voltage level reduces the noise margins of the cells, and may cause loss of the data stored in the cell itself, therein negatively affecting the data retention of the memory.
To maximise the standby power reduction, it is crucial to find this minimum voltage. Two known techniques exist for determining a minimum voltage level: the design-time approach and the run-time approach.
Design Time Approach
With the design time approach, a designer can set the minimum voltage level when designing the integrated circuit. In this open-loop approach, first the theoretical minimum voltage level is determined for the given design. The fixed minimum voltage is then calculated by adding a voltage margin to this theoretical minimum. As the minimum voltage level is fixed for a given design, this voltage margin must be chosen sufficiently large to account for: (i) variations in technology over time and from one foundry to another; (ii) variations in the supply voltage and in operating temperature; and (iii) any parameter variation over the area and the lifetime of the chip. The design time approach has the disadvantage that the voltage margin will be chosen in a very conservative way, and a less optimal reduction in standby power consumption can be obtained.
Run Time Approach
In the run time approach, the minimum voltage level is determined directly on-chip, after manufacturing. Calhoun et al discloses in “standby power reduction using dynamic voltage scaling and canary flip-flop structures” IEEE solid-state circuits vol 39, no 9 September 2004, the use of additional flip-flops to monitor the sensitivity of data retention to Vdd. These so-called canary flip-flops are prone to the same process and environmental changes as the real flip-flops. They can be distributed over the chip to account for variations in process, temperature etc. over the chip area which may occur during manufacturing of the chip. Vdd of these canary flip-flops is progressively reduced until they fail; this minimum value of Vdd is used to indicate the minimum voltage level allowed for the real flip-flops in the memory cells.
An alternative to progressively reduce Vdd on the canary flip-flops is to design an array of different flip-flops, each one designed to fail at a progressively lower Vdd. Identifying the boundary between the failing ones and the working ones makes it possible to determine the critical Vdd level.
Although dynamic at first sight, these approaches still use a Vdd value determined only once, when the chip is manufactured and tested. Moreover, this approach only indicates if failure occurs or not, without giving any indication about the cause of failure nor about the achievable noise margin.
Other run-time approaches to reduce Vdd exist, such as raising the grounding voltage or substrate bias of the memory circuit. Changing the substrate bias will affect the threshold voltage. US2004/0090820 discloses a method for reducing the standby power by increasing the ground voltage Vss of the transistors, e.g. by adding a diode in between the SRAM and the ground supply voltage. US2005/0128789 discloses a sleep mode controller to provide a reduced high supply voltage Vdd and an increased low supply voltage Vss during standby mode. None of these applications discloses a criterion to determine or monitor the optimum value of the reduced supply voltages.